1. Field of the Invention
This invention is related to the field of phase locked loops (PLLs).
2. Description of the Related Art
PLLs are used in a wide variety of applications. In integrated circuits, especially modern integrated circuits operating at high clock frequencies, PLLs are often used to generate the internal clocks for the integrated circuit and to lock the internal clocks to the phase of the clock supplied externally. Phase locking the internal clock to the external clock may aid in providing reasonable setup and hold times for communications on the pins of the integrated circuit. PLLs are also used for clock recovery, data transmission/reception, etc.
Integrated circuits are often designed to be scaleable to different clock frequencies, allowing the integrated circuits to be marketed at different frequency levels/price points and enhancing the usefulness of the integrated circuit in a variety of systems. Accordingly, it is desirable for PLLs to operate properly over a wide range of frequencies while achieving a high degree of noise rejection and fast lock times (the amount of time needed to lock the phase of the internal clock to the external clock).
A PLL may include a voltage regulator for providing a regulated voltage to one or more PLL components (e.g. a charge pump, a voltage controlled oscillator, etc.). The PLL components may be noise sensitive components, and the regulated voltage may reduce noise received from the power supply. Additionally, a level shifter may be coupled between the PLL components and a phase/frequency detector. The level shifter may be supplied by the regulated voltage from the voltage detector. The level shifter may thus attenuate noise present on the input signals to the level shifter, isolating the PLL components from the noise. Noise rejection in the PLL may thus be provided.
In another implementation, a PLL may include a programmable charge pump and a programmable loop filter. For example, the reference current to the charge pump may be changed, thus changing the rate at which the charge pump can change an output voltage (the control voltage to a voltage controlled oscillator in the PLL). The loop filter components may be changed to change the frequency ranges filtered by the loop filter. Accordingly, the PLL response may be adjusted for more optimal operation at a given operation frequency. The flexibility of the PLL for use over a wide range of operating frequencies may thus be enhanced.
Broadly speaking, a PLL is contemplated. The PLL includes a voltage regulator configured to provide a regulated voltage; a phase/frequency detector supplied by a second voltage different from the regulated voltage; one or more PLL components supplied by the regulated voltage; and a level shifter coupled between the phase/frequency detector and the PLL components and supplied by the regulated voltage.
Additionally, a method comprising is contemplated. A regulated voltage is supplied to one or more phase locked loop (PLL) components. A second voltage different from the regulated voltage is supplied to a phase/frequency detector of the PLL. The PLL components are isolated from the phase/frequency detector with a level shifter which also shifts an output of the phase/frequency detector from the second voltage domain to the regulated voltage domain.
Furthermore, a PLL is contemplated, comprising a charge pump configured to provide a voltage on an output node; and a loop filter coupled to the output node. A rate at which the charge pump is able to change the voltage is programmable and frequencies filtered by the loop filter are programmable.
Still further, a method is contemplated. A charge pump in a PLL is programmed. The programming including setting a rate at which the charge pump is able to change a voltage at an output of the charge pump. A loop filter in the PLL is also programmed, the programming includes setting frequencies filtered by the loop filter.